This invention relates to circuitry used in an output data path of an integrated circuit and, in one particular example, to a scheme for an output data path suitable for use in a memory device.
Memory circuits are commonly organized into an array of memory cells arranged in rows and columns. FIG. 1 illustrates the general organization of such memory circuits in which row addresses are used to select word lines and column address are used to select bit line pairs to access the correct cell in a memory array. The memory array is connected to sense amplifiers via the bit lines. The sense amplifiers are designed to sense the logic state of a selected memory cell and provide an amplified signal, representing cell data, to output drivers via the local bus lines. The output drivers are then connected to a global bus. These output drivers are designed to enhance the amplitude of the sense amplifier output signal; to level shift the sense amplifier output signal in order to interface with a different voltage level; and to drive global bus loads.
A control circuit is used to activate the path on which data from a particular cell is read out. The sense amplifier connected to the desired cell is selected and the corresponding bit lines carry the cell data to the selected sense amplifier where the logic state of the cell is detected and read onto the local bus. At the same time, the output driver corresponding to the selected sense amplifier is activated causing the logic state on the local bus to be passed on to the global bus. Based on the signal received from the sense amplifier, the output driver either outputs a logic high or a logic low. However, when a sense amplifier is deselected (i.e., not originally selected or deselected because a different sense amplifier is selected corresponding to a different cell location) then the output driver corresponding to the deselected sense amplifier tristates so that its connection to the global bus does not affect the signal of the selected output.
One type of memory circuit uses complementary outputs from the memory array and, thus, complementary bit lines are available as inputs to the sense amplifiers. A differential sense amplifier is used to sense the difference in signal levels on the complementary bit lines in order to determine the logic state of a memory cell. The logic state is then provided to the global bus on a differential output data path through an output driver.
The memory circuit illustrated in FIG. 1 uses a differential signal on a bit line pair 10 to provide the sensed state of a memory cell to the output driver. Use of a differential signal provides better noise immunity which is advantageous in fast memory circuits were a greater amount of noise is generated due to faster switching. Furthermore, a differential signal allows for encoding four states: logic high, logic low, and two high impedance states. As such, if both bit lines are high (11) or both lines are low (00) then the output driver can be signaled to tristate. At the beginning of a read cycle, the output driver is tristated by taking the line pair corresponding to each bit (initially 01 or 10) to an intermediate logic state (00 or 11). Data is then switched between logic levels during this intermediate period when the output driver is tristated so that any glitch caused by this operation is thereby ignored. The new data, when available, is transitioned on one line only to the opposite state in order to enable the output driver. A complete read cycle, however, takes two global data line transitions.
One problem with such a system is that two bit lines are needed to carry the differential signal. This requires more space than a single bit line and, thus, increases the size of the memory circuit. Another problem is that because of two global data transitions per cycle, the current consumption is increased due to additional line capacitance switching.
Another memory circuit, illustrated in FIG. 2, uses only a single bit line 210 to provide the cell state from the sense amplifier to the output driver. A single bit line, however, can only encode two states: logic high and logic low. Thus, tristate information cannot be carried on a single bit line. Although this arrangement is more space efficient, it makes sensing the cell state more difficult since a differential input signal is not available. In such a memory circuit, a separate line 220 is used to tristate the output driver when the data on the bit line is switched between logic states.
One problem with using a separate tristate line is that it can create a race condition. A race condition occurs when, due to different skews on the bit line and tristate line paths, data on the bit line switches logic states before or after the output driver is signaled to tristate. This condition results in a failure to properly read a memory array cell.
One solution these problems is to increase the amount of time the output driver is tristated in order to increase the chance that the bit line switches logic states within the tristate window. Although the use of a longer tristate window may decrease the chance of a race condition, it slows down the speed of the memory circuit. For example, if the data on the bit line switches immediately after the start of the tristate window, then from that point in time to the end of the window the output driver remains idle.
Yet another problem with such systems is glitching that occurs on the global bus during memory cell address switching. The global bus has a large capacitance due to its extensive length. In order to reduce the need for a large current to drive this large capacitance, the local bus (running parallel to the memory array and collecting data from the sense amplifiers) is partitioned into smaller sections referred to as local bus lines. Data on the local bus lines is then multiplexed onto the global bus line. When selecting a memory cell in a memory array location different from a previously selected cell (with a different corresponding local bus), the global bus may momentarily change states depending on the states currently residing on the local buses. This glitch condition occurs when changing between two local buses corresponding to different memory array locations where the two local bus lines initially possess different logic states and then possess the same logic state when new data is accessed from the memory array.
The following example illustrates a glitch that may occur on the global bus when switching between local bus lines. For this example, assume the global bus was previously carrying a logic 0 and the newly selected data to be placed on the global bus is also a logic 0. The local bus line B0 that was previously active carried a logic 0 and the newly selected local bus line B1 (corresponding to the newly selected data cell) was previously carrying a logic 1. As the new data becomes available (i.e., as the sense amplifier corresponding to B1 becomes active) the output circuit of B1 outputs its data as it is changing states from a logic 1 to a logic 0. Thus, instead of keeping the data on the global bus constant at a logic 0, the global bus is momentarily switched to a logic 1 (the previous state of the B1 output driver as it becomes active) before it receives the newly selected logic 0 data.
As a result of these glitches, current consumption is increased because the memory circuit is forced to charge and discharge the capacitance of the global line due to its momentary change in state. Furthermore, data access time is increased to allow time for the glitches to dissipate.
One solution to the problem is to increase the amount of time the output circuit is tristated in order to decrease the chance that a glitch appears on the global bus. As discussed above, the use of a longer tristate window is not desirable because it may slow down the overall speed of the memory circuit.
Accordingly, it is desirable to have a circuit that allows for use of a single ended output data path while addressing bus glitching and race conditions without significantly reducing access times.
The present invention provides an output data path including a feedforward portion that may be configured to drive a data signal from a selected local bus line onto a global bus and a feedback portion that may be configured to drive the data signal from the global bus onto a deselected local bus line. A first sense amplifier may be configured to drive the data signal onto the selected local bus line. A second sense amplifier may be coupled to the deselected local bus line and may be configured to tristate.
In one embodiment, an output circuit is provided that includes a first driver having a data input coupled to receive a first data, a control input coupled to receive a block control signal, and an output. A second driver, which may be included in the output circuit, may have a data input coupled to receive a global bus data, an inverted control input coupled to receive the block control signal, and an output. The output of the second driver may be coupled to the data input of the first driver, the data input of the second driver may be coupled to the output of the first driver, and the control input of the first driver may be coupled to the inverted control input of the second driver.
In another embodiment, the second driver may tristate and the first driver may be active if the block control signal is a first value, and the first driver may tristate and second driver may be active if the block control signal is a second value.
In yet another embodiment, the output circuit also includes a first local bus line having the first data, a second local bus line having a second data, and a global bus having the global bus data. A third driver which may also be included in the output circuit may have a data input coupled to receive the second data, a control input coupled to receive the block control signal, and an output. A fourth driver which may also be included in the output circuit may have a data input coupled to receive the global bus data, an inverted control input coupled to receive the block control signal, and an output. The output of the fourth driver may be coupled to the data input of the third driver. The data input of the fourth driver may be coupled to the output of the third driver. The control input of the third driver may be coupled to the inverted control input of the fourth driver.
In another embodiment, the second and the third drivers may tristate, the first driver may output the first data onto the global bus line, and the fourth driver may output the global bus data onto the second local bus line if the block control signal is a first value. The first and the fourth drivers may tristate, the third driver may output the second data onto the global bus line, and the second driver may output the global bus data onto the first local bus line if the block control signal is a second value.
Additional features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.